01 / ARTIFACT
Floorplan
Block geometry, boundaries, routing pressure, and open issues.
A clearer path to silicon.
Evidence at every step.
We're building an EDA agent that carries design intent from specification to GDS and checks every handoff. Engineers own the decisions.
DESIGN ROUTE / CONCEPTUALSPEC → GDS
Specification + acceptance contractINPUT / 00
GDS + evidence packageChecks, reports, lineage, open issues
CHECK / DIAGNOSE / REVISE / REVIEW
Backed by
The system
A chip is a chain of decisions. The agent should see the whole chain.
A specification is not a layout recipe. Its intent must survive RTL, synthesis, timing, and layout.
We're building a loop that checks each handoff, traces failures, and proposes bounded fixes. Engineers define acceptance and retain signoff.
See the target workflowContract
Make intent executable.
Set behavior, interfaces, constraints, technology, and acceptance gates before optimization.
Action
Change one thing with purpose.
Propose one bounded RTL or flow change. Record why, then test an isolated candidate.
Judgment
Let evidence decide.
Independent checks protect correctness. Comparable PPA results guide the next experiment.
Target workflow
One route forward. Many ways back.
The target loop ties each stage to inputs, checks, and a next action. Failed gates point to the stage that needs correction.
SPEC TO GDS / TARGET WORKFLOWSEQUENCE + FEEDBACK
00 / DEFINE
Specification
Requirements, architecture, interfaces, budgets, target and acceptance contract
OUT / DESIGN CONTRACT01 / CREATE
RTL + verification
Logic, tests, assertions, lint and functional or formal evidence
OUT / TESTED RTL02 / MAP
Synthesis
Technology mapping, constraints, netlist and equivalence checks
OUT / MAPPED DESIGN03 / IMPLEMENT
Physical design
Floorplan → placement → clock tree → routing and extraction
OUT / PHYSICAL DATABASE04 / REVIEW
GDS + handoff
Layout, reports, open issues and qualified signoff review
OUT / REVIEW PACKETCONTINUOUS EVIDENCE GATESCheck the artifact. Diagnose the failure. Revise the right stage.
Tool completion, functional correctness, physical qualification, and PPA attainment are separate verdicts. A failed or missing mandatory check blocks acceptance.
AGENT PROPOSES + RUNS BOUNDED EXPERIMENTSENGINEERS OWN ACCEPTANCE + HUMAN SIGNOFF
Engineering experience
Chip tapeout experience behind every review.
Our engineers have led multiple chip tapeouts. That experience shapes the proposed workflow's design reviews and acceptance criteria.
Prior team experience
Past team experience, not company partnerships or endorsements.
- Intel
- Meta
- Broadcom
Design and results review
One candidate. Full evidence.
Review handoff checks beside floorplan, performance, and emulation previews. This is an illustrative review surface, not measured agent output.
DESIGN DECISION FRAMEWORKCONTRACT / ARTIFACT / VERDICT
A finished run is not a passing design.Mandatory checks decide which candidates advance.
HANDOFFEVIDENCE TO CAPTUREREVIEW GATE
Spec → RTLBehavior, tests, interfaces, assumptionsCorrectness
RTL → layoutSource, constraints, libraries, lineageEquivalence
Layout → GDSTiming, power, area, physical checksQualified review
TEAM EXPERIENCE: MEASURED SILICON DATA FROM SUB-5 NM PROCESS TAPEOUTS.
RESULTS PREVIEWILLUSTRATIVE / NO MEASURED VALUES
02 / ANALYSIS
Performance
Timing, power, and area against the agreed constraints.
03 / TRIALS
Emulation
Workloads, assumptions, and observed system behavior.
Technical evaluation
Start with one bounded design task.
Pick one block and one handoff. Compare the unchanged tool flow, simple search, and agent-guided runs against the same checks and budget. Count every attempt.
- 01
Define the design, technology, stage, and permitted changes.
- 02
Agree on independent checks, PPA metrics, and tool budget.
- 03
Review qualified results, failures, engineer effort, and gaps.